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| data shift register gain programmable a ca tv line driver ad8321 features functional block diagram linear in db gain response over >53 db range drives low distortion >11 dbm signal into 75 ? load: vcc gnd C53 dbc sfdr at 42 mhz applications gain programmable line driver hfc high speed data modems interactive catv set-top boxes catv plant test equipment ad8321 power- down/ switch inter attenuator core inv data shift register data latch pwr amp daten clk reverse amp sdata general p u r pose if variable gain block description the ad8321 is packaged in a low cost 20-lead soic, operates t he ad8 321 is a low cost digitally controlled variable gain from a single +9 v supply, and has an operational temperature amplifier optimized for coaxial line driving applications such as range of C40 c to +85 c. c able modems that are designed to the docsis * (upstream) very low output noise level maintains constant 75 ? output impedance power-up and power-down condition no line transformer required vin+ upper bandwidth: 235 mhz (min gain) vinC 9v single supply operation power-down functionality supports spi interface low cost vout pd standard. an 8-bit serial word deter m ines the desired output gai n over a 53.4 db range, resulting in gain changes of 0.75 db/lsb. C40 the ad8321 comprises a digitally controlled variable attenuator of 0 db to C53.4 db, which is preceded by a low noise, fixed C50 f o = v in = (p in = 4 137mv C15db 2mhz p-p m) (p out max = 11d gain) bm @ hd3 hd2 gain buffer and followed by a low distortion high power ampli- fier. the ad8321 accepts a differential or single-ended input signal. the output is specified for driving a 75 w load, such as coaxial cable, although the ad8321 is capable of driving other loads. performance of C53 dbc is achieved with an output level up to 11 dbm at 42 mhz bandwidth using a 9 v supply. distortion C dbc C60 C70 a key performance and cost advantage of the ad8321 results from the ability to maintain a constant 75 w output impedance during power-up and power-down conditions. this eliminates the need for external 75 w termination, resulting in twice the effective output voltage when compared to a standard opera- tional amplifier, thus eliminating the need for a transformer. * data-over-cable service interface specifications rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. C80 C90 0 8 1 6 24 32 40 48 56 64 72 gain control C decimal figure 1. harmonic distortion vs. gain control one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/461-3113 ? 2005 analog devices, inc. all rights reserved. (@ v cc = +9 v, t a = +25 ? c, v in = 0.137 v p-p, single-ended input, r l = 75 ? , r in = ad8321Cspecifica tions 75 ? unless otherwise noted) parameter conditions min typ max unit input characteristics specified ac voltage output = 11 dbm, max gain 0.137 v p-p noise figure max gain, f = 10 mhz 15 db input resistance single-ended input 820 w differential input 900 w input capacitance 2.0 pf gain control interface gain range 52.4 5 3.4 54.4 db maximum gain 25.25 26 26.75 db minimum gain C28.15 C27.4 C26.4 d b gain scaling factor 0.7526 db/lsb output characteristics bandwidth (C3 db) a ll gain codes 120 mhz bandwidth roll-off f = 65 mhz 0.8 db bandwidth peaking f = 65 mhz 0 d b output offset voltage all gain codes, full temperature range 30 mv output noise spectral density max gain, f = 10 mhz 60 nv/ hz min gain, f = 10 mhz 20 nv/ hz output noise temperature sensitivity 0 t a +70 c, min gain 0.02 nv/ hz/ c power-down spectral density 1 nv/ hz 1 db compression point max gain, f = 10 mhz 19.5 dbm output impedance power-up and power-down 6 0 7 5 9 0 w overall performance worst harmonic distortion f = 42 mhz, p out = 11 dbm, v cc = +9 v C53 dbc f = 65 mhz, p out = 11 dbm, v cc = +9 v C51 dbc distortion temperature sensitivity C40 c t a +85 c 0 .03 dbc/ c gain accuracy f = 10 mhz, all gain codes 0.2 d b gain temperature sensitivity 0 t a +70 c 0.004 db/ c output settling to 1 mv gain change @ t daten = 1 m in to max gain, v in = 0 v 6 0 n s input change max gain, v in = 0.15 v step 30 ns signal feedthrough power down, 65 mhz, min gain C80 dbc v in = 0.137 v p-p power control power-down settling time to 1 mv max gain, v in = 0 4 0 n s power-up settling time to 1 mv max gain, v in = 0 300 ns power-up/down pedestal offset max gain, v in = 0 30 mv power-up/down glitch max gain, v in = 0 4 0 mv p-p power supply quiescent current power-up, v cc = +9 v 8 2 9 0 9 7 m a power-down, v cc = +9 v 4 5 5 2 6 0 m a specifications subject to change without notice. C2C rev. a ad8321 logic inputs (ttl/cmos logic) ( daten , clk, sdata, v cc = +9 v; full temperature range) parameter min typ max unit logic 1 voltage logic 0 voltage logic 1 current (v inh = 5 v) clk, sdata, daten logic 0 current (v inl = 0 v) clk, sdata, daten logic 1 current (v inh = 5 v) pd logic 0 current (v inl = 0 v) pd 2.1 0 0 C600 50 C250 5.0 0.8 2 0 C100 190 C30 v v n a na m a m a timing requirements (full temperature range, v cc = +9 v, t r = t f = 4 ns, f clk = 8 mhz unless otherwise noted.) parameter min typ max unit clock pulsewidth (t wh ) clock period (t c ) setup time sdata vs. clock (t ds ) setup time daten vs. clock (t es ) hold time sdata vs. clock (t dh ) hold time daten vs. clock (t eh ) input rise and fall times, sdata, daten , clock (t r , t f ) 1 6.0 3 2.0 5.0 1 5.0 5.0 3.0 1 0 ns ns ns ns ns ns n s specifications subject to change without notice. t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) t off t gs analog output signal amplitude (p-p) pd pedestal clk sdata daten t on t c t wh valid data word g2 figure 2. serial interface timing valid data bit msb msb-1 msb-2 t ds t dh sdata clk figure 3. sdata timing rev. a C3C ad8321 absolute maximum ratings * pin configuration supply voltage +v s pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 v input voltages sdata pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v clk pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . C0.8 v to +5.5 v daten internal power dissipation gnd small outline (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 w byp1 operating temperature range . . . . . . . . . . . C40 c to +85 c pd storage temperature range . . . . . . . . . . . . C65 c to +150 c vcc lead temperature, soldering 60 seconds . . . . . . . . . . +300 c vcc * stresses above those listed under absolute maximum ratings may cause perma- vcc nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational vout section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad8321 gnd gnd vinC vcc byp2 gnd gnd vcc gnd vin+ model temperature range package description ? ja package option ad8321ar ad8321ar-reel AD8321ARZ 2 AD8321ARZ-reel 2 ad8321-eval C40 c to +85 c C 4 0 c to +85 c C40 c to +85 c C40 c to +85 c 20-lead soic 20-lead soic 20-lead soic 20-lead soic evaluation board 5 8 c/w 1 5 8 c/w 1 5 8 c/w 1 5 8 c/w 1 r-20 r-20 r-20 r-20 1 thermal resistance measured on semi standard 4-layer board. 2 z = pb-free part. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8321 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions pin function description 1 sdata serial data input. this digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the msb (most significant bit) first. 2 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. a logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. this requires the input serial data word to be valid at or before this clock transition. 3 daten data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0-to- 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previ- ous gain state) and simultaneously enables the register for serial data load. 4, 11, 12, 13, 15, 16 gnd common external ground reference. 5 byp1 v cc /2 reference pin. a dc output reference level that is equal to 1/2 of the supply voltage (vcc). this port should be externally ac-decoupled (0.1 m f capacitor). for external use of this reference voltage, buffering is required. 6 pd power-down low logic input. a logic 0 powers down (shuts off) the power amplifier disabling the output signal and enabling the reverse amplifier. a logic 1 enables the output power amplifier and disables the reverse amplifier. 7, 8, 9, 17, 20 v c c c o m m o n p ositive external supply voltage. 10 vout output signal port. dc-biased to approximately v cc /2. 14 byp2 internal bypass. this pin must be externally ac-decoupled (0.1 m f capacitor). 18 vin+ noninverting input. dc-biased to approximately v cc /2. for single-ended inverting operation, use 0.1 m f decoupling capacitor between vin+ and ground. 19 vinC inverting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 m f capacitor. C4C rev. a 0 0.3 0.6 70 t ypical performance characteristicsCad8321 f = 65mhz f = 10mhz f = 42mhz 70 30 20 60 output noise C nv/ hz 10 46d 23d 00d 71d 50 40 30 20 10 f = 10mhz pd =1 gain error C db p out C dbm gain C db 0 C10 C0.3 C0.6 C20 C0.9 C30 C40 C1.2 0 8 16 24 32 40 48 56 64 72 0.1 1 1 0 100 1000 0 8 16 24 32 40 48 56 64 72 gain control C decimal frequency C mhz gain control C decimal figure 4. gain error vs. gain control figure 5. ac response figure 6. output referred noise vs. gain control C30 C47 pd = 1 max gain (71d) min gai n (00d) 10 f o = 65mhz v in = 0.137v p-p (p in = C15dbm) (p out = 11dbm @ max gain) hd3 hd2 C59 C80 1 1 0 100 0 8 16 24 32 40 48 56 64 72 5 15 25 35 45 55 65 p in = (p out max C14dbm = 12db gain) m @ p in = (p ou max C15db t = 11dbm @ gain) m p in = (p out max C13dbm = 13db gain) m @ p in = (p ou max C17db t = 9dbm @ gain) m 60 C40 output noise C nv/ hz C50 distortion C dbc distortion C dbc 50 C50 40 C53 C60 30 C56 C70 20 frequency C mhz gain control C decimal fundamental frequency C mhz figure 7. output referred noise vs. figure 8. harmonic distortion vs. figure 9. second order harmonic frequency gain control distortion vs. frequency for various input levels 20 30 C47 C59 C80 p out = 11dbm max gain 22 p in = (p out max C13db = 13db gain) m m @ p in = C 14dbm (p out = ma x g 12dbm ain) @ p in = (p ou max t C15db gain) = 11dbm @ m p in = (p ou max C17db t = 9dbm @ gain) m p out = 11dbm max gain 29 3rd order intercept C dbm 0 C50 28 27 distortion C dbc C20 26 C53 C40 25 24 C56 C60 23 5 15 25 35 45 55 65 41.0 41.4 41.8 42.2 42.6 43.0 5 15 25 35 45 55 65 fundamental frequency C mhz frequency C mhz frequency C mhz figure 10. third order harmonic figure 11. two-tone intermodula- figure 12. third order intercept vs. distortion vs. frequency for various tion distortion frequency input levels rev. a C5C ad8321 34 30 frequency C mhz 1 1 0 100 c l = 10pf c l = 0pf c l = 20pf c l = 50pf max gain p out = 11dbm gain C db 26 22 18 14 5v 75ns max gain v in = 0v p-p 15mv pd v out 5v 75ns min gain v in = 0v p-p 5mv pd v out figure 13. ac response for various figure 14. power up/power down figure 15. power up/power down capacitor loads glitch glitch 5v 150ns v in = 0v p-p max gain tr(clk) = 3ns 7.5mv v out daten clk feedthrough C db C100 0.1 C80 C60 0 1 1 0 100 1000 C40 C20 pd = 0 max gain min gain 0.75v 30ns max gain v in = 0v p-p C 0.137v p-p 200mv v in v out frequency C mhz figure 16. clock feedthrough figure 17. input signal feedthrough figure 18. output settling time due vs. frequency to input change 90 100 1.5v 30ns max gain 0.5v v out v in 85 frequency C mhz 1 1 0 100 pd = 1 pd = 0 90 80 80 pd = 0 pd =1 impedance C ? +i cc C ma 75 70 70 60 65 50 60 40 C50 C25 0 2 5 50 75 100 temperature C ? c figure 19. overload recovery figure 20. output impedance vs. figure 21. supply current vs. frequency temperature C6C rev. a data shift register ad8321 operational description the ad8321 is a digitally controlled variable gain power ampli- fier that is optimized for driving a 75 w cable. as a multifunc- tional bipolar device on a single silicon die, it incorporates all th e analog features necessary to accommodate reverse path (upstream ) h igh speed (5 mhz to 65 mhz) cable data modem requirements. the ad8321 has an overall gain range of approximately 53 db an d is capable of greater than 100 mhz operation at output signal levels exceeding 12 dbm. overall, when considering the devices wide gain range, low distortion, wide bandwidth and variable load drive, the device can be used in many variable gain block applications. vcc gnd vinC ad8321 power- down/ switch inter attenuator core inv data shift register data latch pwr amp reverse amp C20 vout vin+ the gain transfer function is as follows: a v = 26 db C ((71 C code) 0.7526 db) for code 71 a v = 26 db for 71 code 127 a v = 26 db + ((199 C code) 0.7526 db) for 128 code 199 a v = 26 db for 199 code 255 where code is the decimal equivalent of the 8-bit w ord loaded in the ad8321s data latch (see figure 23). 30 20 10 gain C db 0 C10 C30 pd 0 32 64 96 128 160 192 224 256 gain code C decimal figure 23. linear-in db gain vs. gain control the ad8321 is composed of four analog functions in the daten clk sdata figure 22. functional block diagram the digitally programmable gain is controlled by the three-wire spi compatible inputs. these inputs are called sdata (serial data input port), daten (data enable low input port) and clk (clock input port). see pin function descriptions and functional block diagram. the ad8321 is programmed by an 8-bit attenuator word. when a standard 8-bit word is used, the first data bit msb will be shifted out of the 7-bit shift register during the eighth rising clk edge. the lower seven bits will then be loaded into the ad8321s digital decode sec- tion when the daten input is taken high. the gain of the ad8321 is linear in steps of 0.7526 db. the gain transfer function starts at C27.43 db (at decimal code 0) and increases 0.7526 db/lsb. the gain increases up to decimal code 71. at this point the gain is at its maximum level of 26 db. if a decimal word between 71 and 127 is entered, the gain is no l onger incremented and stays at 26 db. since the msb of an 8-bit word is a dont care bit, at decimal code 128, the ad8321s gain returns to its minimum value. the gain vs. gain control relationship repeats itself as shown in figure 23 for the upper 127 codes. power-up or forward mode. the input amplifier (preamp) which can be used single-endedly or differentially and provides a maxi- mum of 12 db of attenuation. if the input is used in the differ- ential configuration, it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes. this will ensure the proper gain accuracy and harmonic performance. the preamp stage drives a vernier stage that provides the fine tune gain adjustment. the 0.7526 db step resolution is imple- mented in this stage. after the vernier stage, a dac p rovides the bulk of the ad8321s attenuation (six bits or 36 db ) . t h e signals in the preamp and vernier gain blocks are differential to improv e the psrr and linearity. a single-ended current is fed from the dac into the output stage, which amplifies this current to the appropriate level necessary to drive a 75 w load. t h e output stage utilizes negative feedback to implement a 7 5 w output i mpedance. this eliminates the need for an external 75 w match- ing resistor needed in typical video (or video filter) termination requirements. rev. a C7C ad8321 the attenuation setting in the ad8321 is determined by the 8-bit word in the data latch. the sdata load sequence is initiated by a falling edge on daten . the gain control data (sdata) is serially loaded (msb first) into the 7-bit shift register at each rising edge of the clock. see figure 24. while daten is low, the data latch holds the previous data word allowing the attenuation level to remain unchanged. after eight clock cycles the new data w ord is fully loa ded and daten is switched high. this enables the data latch and the loaded register data is passed t o the attenuator with the updated gain value. also at this daten transition, the internal clock is disabled, thus inhibiting new serial input data. the power amplifier has two basic modes of operation. a for- ward mode (or power-up mode) and a reverse mode (or power- down) mode. in the power-up mode ( pd = 1), the power amplifier stage is enabled and the ad8321 has a maximum gain of 20 v/v or 26 db (into 75 w ). with a total attenuation of 53.43 db in the dac, vernier and preamp, the ad8321s total gain range is 26 db to C27.43 db. in both the forward or reverse mode the single-ended output signal maintains a dc level of v cc /2. this dc output level provides for optimum large signal linearity. in the power-down mode ( pd = 0), the power amplifier is turned off and a reverse amplifier (the inner triangle in figure 22) is enabled. during this 1-to-0 transition, the output power is disabled. this assures that s11 and s22 remain approximately equal to zero thus minimizing line reflections. in the time domain, as pd switches states, a transitional glitch and pedestal offset results (see figures 14 and 15). these anomalies have been minimized by t e m perature compensated internal circuitry and la ser trimming. the powered down supply current drops to 52 ma versus 90 ma i n the power-up mode. sdata clk daten pd analog output t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) valid data word g2 t off t gs signal amplitude (p-p) pedestal t c t wh figure 24. serial interface timing applications general application the ad8321 is primarily intended for use as the return path (also called upstream path) power amplifier (pa) or line driver in cable modem applications. upstream data is modulated in either qpsk or qam format. this is done either in dsp or by a dedicated qpsk/qam modulator such as the ad9853 or other modem/modulator chip. the amplifier receives its input signal either from the dedicated qpsk/qam modulator or from a dac. in both cases, the signal must be low-pass filtered before being applied to the line driving amplifier. because the dist ance to the central office varies from cable modem s u b - scriber to subscriber, resulting in various line losses, signals from various subscribers will require attenuation while others may require gain. as a result, the ad8321 line driver is required to vary its output applying attenuation or gain as needed so that all signals arriving at the central office are of the same amplitude. docsis (data over cable service interface specifications) requires a cable modem output signal ranging in power from a minimum of 8 dbmv to a maximum of 58 dbmv. in cable modem applications where docsis compliance is desired, the ad8321 amplifier must be used in conjunction with a 75 w matching attenuator connected between the ad8321 output and the low-pass input port of the diplexer. see the schematic i n figure 28. the matching attenuator is used to achieve docs i s - compliant noise levels at the lower end of the ad8321 output power range. the insertion loss of a diplexer is typically less than 1 db. as a result of these combined losses, the pa line driver must be capable of delivering sufficient power into a 75 w load while maintaining reasonable distortion performance at the output of the modem. (see sections containing docsis for further information. all references to docsis pertain to sp-rfi-i04-980724 entitled radio frequency interface specification.) t on C8C rev. a ad8321 basic connection input bias, impedance and termination figure 25 shows the basic schematic for operating the ad8321 on the input side, the vin+ and vinC have a dc bias level in single-ended inverting mode. to operate in inverting mode, e qual to (v cc /2) C 0.2 v. the input signal must therefore be connect the input signal through an ac coupling capacitor to ac -coupled before being applied to either input pin. the input vinC; vin+ should be decoupled to ground with a 0.1 m f impedance, when operated in single-ended mode is roughly capacitor. because the amplifier operates from a single supply, 820 w (900 w in differential mode). an external shunt resis- and the differential input pins are biased to approximately tance (r1) to ground of 82.5 w is required to create a single- v cc / 2, the differential inputs must be ac-coupled using 0.1 m f ended input impedance of close to 75 w . if single-ended 50 w capacitors. for operation in the noninverting mode, the vinC termination is required, a 53.6 w shunt resistor may be used. pin should be decoupled to ground via a 0.1 m f capacitor, with differential input operation may be achieved by using a shunt t he input sig nal being fed to the ad8321 through the (ac-coupled) r esistor of 41 w to ground on each of the inputs, or 82.6 w vin+ pin. inverting mode should be chosen if the ad8321 is across the inputs resulting in a differential input impedance of being used as a drop-in replacement for the ad8320 (the approximately 75 w . note: to avoid dc loading of either the ad8321 predecessor). balanced differential inputs to the vin+ or vinC pin, the ac-coupling capacitor must be placed ad8321 may also be applied at an amplitude that is one-half between the input pin(s) and the shunt resistor(s). refer to the the specified single-ended input amplitude. see the differential differential inputs section for more details on this mode of inputs section for more on this mode of operation. operation. power supply and decoupling output bias, impedance and termination the ad8321 should be powered with a good quality (i.e., low on the output side, the vout pin is also dc-biased to v cc /2 or noise) single supply of 9 v. although the ad8321 circuit will midway between the supply voltage and ground. the output function at voltages lower than 9 v, optimum performance will signal must therefore be ac-coupled before being applied to the not be achieved at lower supply settings. careful attention must load. the dc-bias voltage is available on the byp1 and byp2 be paid to decoupling the power supply pins. a 10 m f capacitor pins (pins 5 and 14 respectively) and can be used in dc-biasing located in near proximity to the ad8321 is required to provide schemes. these nodes must be decoupled to ground using a good decoupling for lower frequency signals. in addition, and 0.1 m f capacitor as shown in figure 25. if the byp1 and/or more importantly, five 0.1 m f decoupling capacitors should be byp2 voltages are used externally, they should be buffered. located close to each of the five power supply pins (7, 8, 9, 17, external back termination resistors are not required when using and 20). a 0.1 m f capacitor must also be connected to the pins the ad8321. the output impedance of the ad8321 is 75 w and labeled byp1 and byp2 (pins 5 and 14) to provide decoupling is maintained dynamically. this on chip back termination is to internal nodes of the device. all six ground pins should be maintained regardless of whether the amplifier is in forward connected to a common low impedance ground plane. transmit mode or reverse powered down mode. if the output s ignal is being evaluated on 50 w test equipment such as a spectrum a nalyzer, a 75 w to 50 w adapter (commonly called a minimum loss pad) should be used to maintain a properl y matched circuit. attenuator core data shift register data latch ad8321 power- down/ switch inter daten clk vin+ vinC pd vout sdata vcc vcc c8 0.1 ? f vcc c9 0.1 ? f vcc c10 0.1 ? f vcc c11 0.1 ? f byp1 c5 0.1 ? f c2 0.1 ? f c1 0.1 ? f r1 82.5? input daten clk gnd gnd gnd gnd gnd sdata c4 0.1 ? f to diplexer r in = 75? byp2 vcc +9v ce 0.1 ? f c6 10 ? f c7 0.1 ? f figure 25. basic connection for single-ended inverting operation rev. a C9C ad8321 varying the gain and spi programming the gain of the ad8321 can be varied over a range of 53 db from approximately C27 db to +26 db, in increments of approximately 0.7526 db per lsb. programming the gain of the ad8321 is accomplished using conventional serial peripheral interface or spi protocol. three digital lines, daten , clk and sdata, are used to stream eight bits of data into the serial shift register of the ad8321. changing the state of the daten port from logic 1-to-0 starts the load sequence by activating the clk line. no changes in output signal are realized during this transi- tion. subsequently, any data applied to sdata is clocked into the serial shift register most significant bit (msb) first and on the rising edge of each clk pulse. the ad8321 may be pro- grammed to deliver maximum gain (+26 db) at decimal code 71. as a result, only the last seven bits of a typical 8-bit spi word effect the gain resulting in the gain response depicted in figure 22. since the spi codes from 0 through 71 appear digi- tally identical to codes 128 through 199 for all bits except the msb, the ad8321 repeats the gain vs. decimal code response twice in the 256 available codes (see operational description for gain equations and figure 23 for gain response). the msb of a typical spi word (i.e., the first data bit presented to the sdata line after the daten transition from logic 1 to 0 and prior to t he rising edge of the first clock pulse) is disregarded or ignored. data enters the serial shift register through the sdata port on the rising edge of the next seven clk pulses. returning the daten line to logic 1 latches the content of the shift register into the attenuator core resulting in a well controlled change in output signal level. the timing diagram for ad8321s serial interface is shown in figure 24. gain dependence on load impedance the ad8321 has a dynamic output impedance of 75 w . this dynamic output impedance is trimmed to provide a maximum gain of +26 db when loaded with 75 w . operating the ad8321 at load impedances other than 75 w will only change the gain of th e ad8321 while the specified gain range of 53 db is unchanged . varying the load impedance will result in 6 db of additional gain w hen r load approaches infinity. the relationship between r load and gain is depicted in figure 26 and is described by the following equation: gain ( db ) = [20 log ((2 r load )/( r load +75))]+(26C(0.7526 (71- code ))) 35 30 25 20 15 10 5 0 0 100 200 300 400 500 r load C ? figure 26. maximum gain vs. r load gain C db between burst on/off transients, asynchronous power- down and docsis a 42% reduction in consumed power may be achieved asynchro- no usly by applying logic 0 to pd pin 6 activating the on-chip reverse amplifier. the supply current is then reduced to approximately 52 ma and the modem can no longer transmit in t he upstream direction. the on-chip reverse amplifier is designed to reduce between burst noise and maintain a 75 w source impedance to the low pass port of the modems diplexer while minimizing power consumption. changing the logic level applied to the pd pin will result in a burst on/off transient at the output of the ad8321. the transient results from switching between the forward transmit amplifier and the powered down (reverse) amplifier. although the resulting transient meets the docsis transient amplitude requirements at maximum gain, it is the lower gain range (i.e., 8 dbmv to 31 dbmv) where the a d8321 may exceed the 7 mv maximum. the diplexer may further reduce the glitch amplitude. an external rf switch, such as alpha industries as128-73 gaas 2 watt high linearity spdt rf switch, may be used to further reduce the spurious emissions, improve the isolation between the cable plant and the upstream line driver and switch in a 75 w back termination required to maintain proper line termination to the lp port of the diplexer (see figure 28). noise and docsis one of the most difficult issues facing designers of docsis compliant modems is maintaining a quiet output from the pa d uring times when no information is being transmitted upstream . in addition, maintaining proper signal-to-noise ratios serves to ensur e the quality of transmitted data. this is extrem ely critical when the output signal of the modem is set to the minimum docsis specified output level or 8 dbmv. the ad8321 output noise spectral density at minimum gain (or 8 dbmv) is 20 nv/ hz measure d a t 1 0 mhz. considering the spurious emissions in 5 mhz to 42 mhz of table 4C8 in docsis, the calculated noise power in dbmv for 160 k sym/sec is: 2 ? ? 20 log ? 20 nv / hz 160 e + 3 ? ? + 6 0 o r - 4 1 5 ? ? ? . dbmv ? ? comparing the computed noise power to the signal at 8 dbmv yields C49.5 dbc or 3.5 db higher than the required C53 dbc in docsis table 4C8. an attenuator designed to match the ad8321 75 w source to the 75 w load may be required. refer- rin g to the schematic of figure 28 and the evaluation board silkscreen of figure 31, the matching attenuator is comprised of the three resistors referred to as rc, rd and re. select the at- tenuation level from table i such that noise floor is reduced to levels specified in docsis. table i. rc ( ? ) rd ( ? ) re ( ? ) attenuation (db) 1304 8.65 1304 C1 654.3 17.42 654.3 C2 432 26.1 432 C3 331.5 35.75 331.5 C4 C10C rev. a ad8321 distortion and docsis care must be taken when selecting attenuation levels specified in table i as the output signal from the ad8321 must compen- sate for the losses resulting from any added attenuation as well as the insertion losses associated with the diplexer. an increase in input signal becomes apparent at the upper end of the gain range and will be needed to achieve the 58 dbmv at the modem output. the insertion losses of the diplexer may vary, depend- ing on the quality of the diplexer and whether the frequency of operation is in near proximity to the cut-off fre quency of the low-pass filter. figures 9 and 10 show the expected second and third harmonic distortion performance vs. fundamental frequency at various input power levels. these graphs indicate the worst harmonic levels exhibited over the entire output range of the ad8321 (i.e., C27 db to +26 db). figures 9 and 10 are u seful w hen it is necessary to determine inband ha rmonic levels (5 mhz to 42 mhz or 5 mhz to 6 5 m h z). harmonics that are higher in frequency, as compared to the cutoff frequency of the low-pass filter of the diplexer, will be further suppressed by the stop band attenuation level of the lp filter in the diplex e r . d esigners must balance the need to improve noise performance by adding attenuation with the resulting need for increased signal amplitude while maintaining docsis specified dis- tortion performance. evaluation board features and operation the ad8321 evaluation board (p/n ad8321-eval) and com- panion software program written in microsoft visual basic are avail able through analog devices, inc. and can be used t o control the ad8321 variable gain upstream power amplifier via the parallel port of a pc. this evaluation package provides a convenient way to program the gain/attenuation of the ad8321 without the addition of any external glue logic. ad8321-eval has been developed to facilitate the use of the ad8321 in an application targeted at docsis compliance. a low cost alpha industries as128-73 gaas 2 watt high linearity spdt rf switch (referred to as swb) is included on the evaluation board (see figure 28) along with accommodations for a user specified 75 w matching attenuator (see table i for a table of resistor v alues of attenuators ranging from C1 db to C4 db). the ad8321 daten , clk and sdata digital lines are pro- grammed according to the gain setting and mode of operation selected using the windows ? interface of the control software ( see figure 30). the serial interface of the ad8321 is ad- dressed through the parallel port of a pc using four or more bits (plus ground). two additional bits from the parallel port are used to control the rf switch(s). this software programs the ad8321 gain or attenuation, incorporates asynchronous control of the power-down feature ( pd pin 6) as well as asyn- chronous control of the alpha industries rf switch(es) as128- 73. * a standard printer cable is used to feed the necessary data to the ad8321-eval board. these features allow the designer to fully develop and evaluate the upstream signal path begin- ning at the input to the pa. overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot. overshoot presented to the clk pin (tp7 on the evaluation board) may cause communications problems. the evaluation board layout was designed to accommodate a series resistor and shunt capacitor (r6 and c12) if required to filter or condition the clk data. between burst transient reduction in order to reduce the amplitude of the burst on/off tran- sient glitch at the output of the ad8321, when switching from forward transmit mode to reverse powered down mode, position the swb switch in figure 28 to position a before changing the logic applied to pd pin 6 of the ad8321 from logic 1-to-0 (and also 0-to-1). use the enable output switch feature in the evaluation board control software (see figure 31) to select the appropriate position of the as128-73 switch. a check in this b ox enables the switch to pass upstream data to the output of the evaluation board. the as128-73 produces a glitch of approxi- mately 5 mv p-p regardless of the ad8321 gain setting. the ad8321-eval board comes with resistors and capacitors in stalled on the logic lines controlling the rf switch (r8, r9, c16, c17). these values were selected to reduce the glitch amplitude to docsis acceptable levels and may be modified if required. the spdt function of the as128-73 rf switch accommodates the need to maintain proper termination when the diplexer is disconnected from the output of the ad8321. the ad8321-eval board accommodates the needed back termination (refer to the cb and rb of the evaluation circuit). differential inputs when evaluating the ad8321 in differential input mode, termi- nation resistor(s) should be selected and applied such that the combined resistance of the termination resistor(s) and the input impedance of the ad8321 results in a match between the signal source impedance and the input impedance of the ad8321. t h e evaluation board is designed to accommodate mini-circuits t 1 - 6t-kk81 1:1 transformer for the purposes of convert ing a single-ended (i.e., ground referenced) input signal to differen- tial inputs. the following paragraphs identify three options for providing differential input signals to the ad8321 evaluation board. option 1 uses a transformer to produce a truly differen- tial input signal. the termination resistor(s) specified in option 1 and 2 may also be used without the transformer if a differen- tial signal source is a v ailable. option 2 uses a transfor mer and- produces ground referenced input signals that are separated in phase by 180 . option 3 relies on differential signals provided by the user and does not employ a transformer for single-to- differential conversion. differential input option 1: install the mini-circuits t1-6t- k k81 1:1 transformer in the t1 location of the evaluation board. jumpers j1, j2 and j3 should be applied pointing in the direction of the transformer. a differential input termination resistor of 82.5 w can be used in the r3 position. this value should be used when the single-ended input signal has a source impedance of 75 w . in this configuration, the input signal must be applied to the vin+/diff in port of the evaluation board. an open circuit is required in r1, r2 and j4 positions resulting in a 75 w differential input termination to the ad8321. if a 50 w single-ended input source is applied to the vin+/diff in port, the r3 value should be 53.6 w . windows is a registered trademark of microsoft corporation. * alpha industries @ www.alphaind.com rev. a C11C ad8321 differential input option 2 : install the mini-circuits t1-6t- k k81 1:1 transformer in the t1 location of the evaluation board. jumpers j1, j2 and j3 should be applied pointing in the direction of the transformer. apply an open circuit in the r3 position while j4 is applied connecting the center-tap of the secondary to ground. a 41 w resistor should be used between each input and ground at r1 and r2. this option w ill also result in a 75 w differential input termination to th e ad8321. if a 50 w single-ended input source is applied to t h e vin+/ diff in port, the r1 and r2 values should be 26.7 w . differential input option 3 : a di fferential input may be a pplied to both vinC and vin+ inputs of the evaluation board. in this example, no transformer is employed. jumpers j1, j2 and j3 are installed in line with the input signals. select the differen- tial input termination configuration of either option 1 or option 2 . apply option 1 resistor value to r3 for a true differential input or apply option 2 values to r1 and r2 to produce ground refer- enced inputs that are separated in phase by 180 . if the differen- tial input signal source impedance is anything other than 75 w or 50 w , calculate the appropriate value according to the equa- tions below: for option 1 configurations: desired input impedance = r 3 ? 900 for option 2 and 3 (r1 = r2 = r): desired input impedance = 2 ( r ? 450) diff in ad8321 r1 r2 ad8321 r3 option 2 differential input termination t1 option 1 differential input termination diff in t1 vin+ vinC r1 r2 ad8321 option 3 differential input termination figure 27. differential input termination options controlling the evaluation board from a pc the ad8321-eval package comes with the circuit described by figure 28 and includes a C2 db attenuator (reference rc, rd and re) and the control software allowing the user to program the gain/attenuation of the ad8321 via a standard printer cable connected to the parallel port of a pc. install software to install the cabdrive software that controls the ad8321- eval evaluation circuit, close all windows applications and select the setup file located on disk 1 of the ad8321- eval software. follow the on screen instructions (see figure 29) and insert disk 2 when prompted to do so. enter the path of the directory into which the control software will be installed. select the button in the upper left corner to begin the installa- tion of cabdrive software into the specified directory. running the software to invoke the control software, select the ad8321 icon from the directory containing the installed software. after invoking the control software, choose the appropriate printer port from the display portrayed in figure 30. controlling the gain/attenuation of ad8321 the ad8321 control panel has four different functions. the slide bar controls the gain/attenuation of the ad8321. adjust the slider to the gain/attenuation displayed in units of db. the additional displays show the selection in units of volts (output)/ volts (input), and the corresponding control codes in decimal, binary and hexadecimal. (see figure 31.) power up and power down the buttons marked power up and power down select the mode of operation of the ad8321. the power up button puts the ad8321 in forward transmit mode feeding the condi- tioned signal to the vout port on the evaluation board. con- versely, the power down button selects the reverse mode where the forward signal transmission is disabled and the low noise reverse amplifier actively maintains a 75 w back termina- tion. these features may be selected asynchronously (at any time). (see the section on between burst transient reduction for more specific details.) enable output switch an alpha industries as128-73 gaas 2w hi linearity switch is installed on a standard ad8321-eval circuit and is controlled by the check box on the control panel portrayed in figure 31. this feature is intended to remove the output of the ad8321 from the vout port prior to using the power up and power down feature described above. this application circuit m ay be used to reduce any transients created between bursts to docsis c o m pliant levels. (see the section on between burst transient reduction for more specific details.) C12C rev. a ad8321 tp1 vinC c14 10 ? f c15 0.1 ? f v ct ad8321 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 c1 0.1 ? f tp4 tp6 sdata tp7 c12 1000pf r6 tp8 daten tp9 c4 c7 c8 c9 tpa cc 0.1 ? f tpc jb vcc clk pd gnd v1 1k? v2 1k? c16 1000pf c17 1000pf p1C7 p1C8 p1C3 p1C2 p1C6 p1C5 r8 r9 c6 10 ? f c10 0.1 ? f v cc tp5 c10 c5 rb c11 c2 0.1 ? f rc re rd v1 v2 75? cb 0.1 ? f b vct tp12 tpd rf 10k? ce 0.1 ? f tpe tp13 as128-73 swb cd 0.1 ? f note: bypass capacitors c4, c5, c7, c8, c9, c10 and c11 are 0.1 ? f. r1 82.5? j3 to diplexer figure 28. ad8321-eval schematic of single-ended inverting input, upstream pa driver solution using ad8321, matching attenuator and alpha industries as128-73 rf switch rev. a C13C ad8321 evaluation board features and operation figure 29. evaluation board software installation figure 30. evaluation board control software C14C rev. a ad8321 figure 31. screen display of windows-based control software rev. a C15C ad8321 figure 32. evaluation board silkscreen (component side) C16C rev. a ad8321 figure 33. evaluation board layout (component side) figure 34. evaluation board layout (solder side) rev. a C17C ad8321 evaluation board bill of materials ad8321 evaluation board rev. b single- ended inverting input march 17, 1999 qty. description vendor ref desc. 2 14 3 1 3 2 1 2 1 1 1 2 1 6 2 3 1 2 2 5 2 1 4 1 1 4 4 2 2 2 2 1 0 m f 16 v. 1350 size tantalum chip capacitor 0.1 m f 50 v. 1206 size ceramic chip capacitor 1,000 pf 50 v. 1206 size ceramic chip capacitor 82.5 w 1% 1/8 w. 1206 size chip resistor 0 w 5% 1/8 w. 1206 size chip resistor 1.00 k w 1% 1/8 w. 1206 size chip resistor 75.0 w 1% 1/8 w. 1206 size chip resistor 649 w 1% 1/8 w. 1206 size chip resistor 10.0 k w 1% 1/8 w. 1206 size chip resistor 17.4 w 1% 1/8 w. 1206 size chip resistor a lpha # as 128-73 gaas hi linearity switch p ink test point b lue test point [vct] g rey test point [bus lines] y ellow test point [inputs] o range test point [outputs] r ed test point [dut vcc] b lack test point [gnd] 2 pin .1 inch ctr. shunt berg # 65474 - 001 2 pin .1 inch ctr. male header berg # 69157 - 102 75 w right-angle bnc telegartner # j01003a1949 c onn. 36 pin centronics right angle 5-way metal binding post ad8321 ar ad8321 rev. b evaluation pc board # 4 - 40 1/4 inch ss panhead machine screw # 4 - 40 3/4 inch long aluminum round stand-off # 2 - 56 3/8 inch ss panhead machine screw # 2 steel flat washer # 2 steel internal tooth lockwasher # 2 ss hex. machine nut ads# 4-7-6 ads# 4-5-18 ads# 4-5-20 d -k # p 82.5 fct-nd ads# 3-18- 88 ads# 3-18-11 ads# 3-18-145 d -k # p 649 fct-nd ads# 3-18-119 d -k # p17.4 fct-nd alpha # as 128-73 ads# 12-18-63 ads# 12-18-62 ads# 12-18-64 ads# 12-18-32 ads# 12-18-60 ads# 12-18-43 ads# 12-18-44 ads# 11-2-38 ads# 11-2-37 comp. mktg. services ads# 12-3-50 ads# 12-7-7 ads# ad8321ar e.m.c. ads# 30-1-1 ads# 30-16-3 ads# 30-1-17 ads# 30-6-6 ads# 30-5-2 ads# 30-7-6 c6 & c14 c1Cc5, c7Cc11, cbCe c12, c16 & c17 r1 r2 & r6, ca r8 & 9 rb rc & re rf rd swb tpc & tpd tp14 tp6Ctp9, tp12 & tp13 tp1 & tp2 tpa, tpb & tpe tp4 tp5 & tp15 j3 & jb j3, ja, jb, jc, jd inputs, output p1 dut vcc, gnd, vct d.u.t. e valuation pc board (p1 hardware) (p1 hardware) (p1 hardware) (p1 hardware) optional components j1, j2, j4, r3, ra, swa, t1, +vin+ C18C rev. a ad8321 outline dimensions 20-lead standard small outline package [soic_w] wide body (r-20) dimensions shown in millimeters and (inches) revision history location page 6/05data sheet changed from rev. 0 to rev. a. changes to orderi ng gui de ...................................................................................................... .............................................. 4 updated outline di mensi ons ..................................................................................................... ........................................ 1 9 rev. a C19C c01013??/05(a) ?0 |
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